［ASML Recruiting］ IC Design Engineer
The job is located in Hsinchu/Tainan that could work on the advanced analog and mixed signal ASIC for next generation electron detection channel for the leading edge e-beam inspection and metrology systems with work life balance.
The following are the Job Descriptions for this opportunity
• Develop the functional blocks of high-speed Analog-to-Digital Converter (ADC) and/or Phase-Locked Loop (PLL) in ASIC for the detection channel of electron beam inspection tools, including:
• Define the design specifications of the Read-Out Integrated Chip (ROIC) or chipset based on product roadmap and System Performance Specifications (SPS) defined by system engineer.
• Develop new circuit architecture and technical solutions for next generation ASICs in detection channel, including feasibility study, schematic design, pre-layout simulation, layout design, and post-layout simulation.
• Cooperate with Printed Circuit Board (PCB) designer to design Evaluation Board (EVB) and with test engineer to test and characterize the ASICs.
• Create Element Design Specifications (EDS) and Test Performance Specifications (TPS) based on detail ASIC design and chip test/verification.
• Cooperate with IC design partner to develop the ASICs for detection channel of of electron beam inspection tools, including:
• Review the detail schematic and layout design, TPS, and test results from our partner during the ASIC industrialization phase.
• Together with the engineering team from the partners, identify design solutions to achieve the specifications of the module/function. Review the design details and simulation results from our partner.
• Support module level and sub-system level integration
• Generate and / or review related IP documents
Provide with more information about the position: D&E - IC Design Engineer - Tainan/Hsinchu - Jobs | ASML
https://www.asml.com/en/careers/find-your-job/2/4/9/de-ic-design-engineer-tainanhsinchu-req24973
d&e asml 在 [請益] A/GG Offer請益- 看板Tech_Job - 批踢踢實業坊 的推薦與評價
板上各位百萬年薪前輩好
以下是小弟目前收到的2個offer與現職比較，想請益大家的意見
N為現職薪水
ASML GG 現職
職務 D&E System Integration CIS RD integration RD integration
待遇 (N+3)*14 +車補5k*12+ bonus (N+3)*14 +bonus N*14 + bonus
地點 台南 台南 台南
工時 9:00~18:00 8:30~20:30 8:30~19:00
很少加班 每日平均加班3hr 每日平均加班1.5h
r
出差 年累計約60天以內 無出差 無出差
輪班 無 假日值班 小夜/假日值
班
(約2個月1次) (約2個月1次
)
加班費 可報加班費 無加班費 可報休假
On call 無 有 有
交通 住家裡，50分鐘 住家裡，50分鐘 住家裡，50分
鐘
以上想請教各位大大們的想法及建議，謝謝!
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